How Does a Microchip Process Instructions?

What you will learn

• Distinguish instruction encoding from input data.
• Follow registers and the arithmetic unit.
• Understand why a processing stage is not automatically a clock cycle.

Before you start

Read the linked prerequisite first. This article explains principles and does not require assembling or opening equipment.

Fetch and decode

Instruction memory supplies an instruction encoding. The decoder reads its bits and produces control signals that coordinate the processor. Operand values are read from the register file.

Think of an instruction as specifying an operation and its inputs. That request differs from the actual values being added or compared. Reading a value without decoding an operation does not say what should happen to it.

• Processing control
• Arithmetic execution

Execute and write back

The arithmetic logic unit performs the requested computation, such as addition or shifting. Loads and stores also access data memory. Not every instruction therefore needs a data-memory read or write.

A result is written back to the register file; a load obtains that result from memory rather than arithmetic. Distinguish an intermediate signal from a stored result available to a later instruction.

Are stages clock cycles?

Architecture determines how work maps to clock cycles. Single-cycle, multi-cycle and pipelined processors organize these responsibilities differently. A pipeline can decode one instruction while fetching another.

A stage diagram explains responsibilities. It does not establish that every real CPU uses one cycle per stage or that all instructions take equal time.

A worked example

Take two illustrative instructions in a simple processor, not a description of any real CPU. The first: “add register A to register B and keep the result in register C”. Instruction memory delivers the encoding to the decoder; the decoder reads the bits and produces control signals, while the two operands are read from registers A and B. The arithmetic unit adds them, and the result is written back to register C. This instruction never touches data memory.

The second: “load a value from data memory into register C”. Fetch and decode look the same as before, but this time data memory is read, and the result written to register C comes from memory rather than from an addition. Place the two side by side to see which parts are shared (fetch, decode, write-back) and which are specific (whether data memory is accessed).

If the processor is pipelined, the decoder may be working on the first instruction while the second is fetched. The order of steps within each instruction stays the same; only the work of different instructions overlaps.

Frequently asked questions

Is an instruction a source-code sentence?

This article concerns the encoding decoded by a processor, without assuming one source-code sentence equals one machine instruction.

Does pipelining skip decoding?

No. It overlaps work belonging to different instructions.

Summary

• Decoding produces control signals from an encoding.
• Operands are processed and results stored.
• Architecture determines how stages map to clock cycles.